1. Field of the Invention
The present invention relates generally to computer systems with direct memory access (DMA) and more particularly to distributed DMA. Still more particularly, the present invention relates to checking for DMA programming cycles that include configuration information that has not changed since the last programming cycles.
2. Background of the Invention
A personal computer (PC) includes numerous electronics components interconnected by a network of "busses." A bus is a collection of digital signal lines over which data, addresses, and control information is transferred from one device connected to the bus to another device on the same bus. A typical PC includes a microprocessor (CPU), memory, and a variety of peripheral devices that may be coupled to the CPU and memory by way of one or more busses. These peripheral devices may include a floppy drive, audio card, and modem, to name a few.
Typically, many devices in a PC require access to memory for storing (referred to as a "write" transaction) and retrieving data (a "read" transaction). The CPU thus runs read and write cycles to memory. The CPU may also read data from memory and then write that data to another device in the computer system. As PC's have become increasingly more sophisticated with additional peripheral devices, the burden on the CPU correspondingly increased. Not only did the CPU run cycles to memory for its own purposes, but the CPU was often called upon to retrieve data from memory on behalf of a peripheral device.
To alleviate the burden on the CPU, PC's were provided with the ability to perform "direct memory accesses" (DMA). A DMA cycle permits a peripheral device to write data to or read data from memory with much less CPU involvement than previously required. When using DMA, the CPU must still initiate the data transfer, but the actual data transfer is handled exclusively by a DMA controller, thereby freeing up the CPU to perform other tasks while the data transfer is taking place. After the DMA controller completes the data transfer, the peripheral device interrupts the CPU to indicate the transfer has completed. DMA transfers are often referred to as "fly-by" operations because the data is passed between the peripheral device and memory in a single DMA cycle, rather than two cycles if the CPU was to perform the transfer (a read of the data in one cycle followed by a write to the destination device in a subsequent cycle).
Early PC's included one DMA controller that provided four channels (referred to as channels 0-3) where each DMA channel could be used by a separate peripheral device to handle data transfers with memory. A second DMA controller was added to provide additional DMA channels in a cascaded arrangement. The two DMA controllers were cascaded together, one of the DMA controllers was designated as having channels 0-3 and the other controller had channels 4-7. Channels 0-3 were used for byte (8 bits) transfers and channels 5-7 were used for word (16 bit) transfers. Channel 4 was used for cascading the two controllers together and, therefore, was not available for normal DMA data transfers. The word-wide DMA controller was sometimes referred to as the "primary" or "master" DMA controller, while the byte-wide DMA controller was referred to as the "secondary" or "slave" DMA controller. DMA systems based on this architecture are referred to as "legacy" DMA systems.
The Industry Standard Architecture (ISA) bus and the Extended Industry Standard Architecture (EISA) bus are busses commonly found in many PC's. These busses include signals for performing DMA operations. A peripheral device connected to the ISA bus may request a DMA operation by providing a DMA request signal (DRQ*, where * indicates the channel number) over the ISA bus to the DMA controller. In response to a DRQ signal, the DMA controller will provide a DMA acknowledge (DACK*) signal to the peripheral device when the DMA controller has been granted the ISA bus and is ready to perform the operation. The DMA controller then accesses the peripheral to move data over the ISA bus and between the peripheral and memory. However, since the PCI bus does not incorporate the ISA DMA signals, the ISA DMA devices cannot be placed on these busses.
The PCI is a popular bus because of its performance is generally superior to that of the ISA bus. As such, it is desirable to connect many of the ISA peripherals directly to the PCI bus instead of the ISA bus. The incompatibility between the ISA DMA controller architecture and the PCI bus prevents the joining of these components.
In certain systems, such as portable computers, the limited space requirements allow only one expansion bus to be supported. If only the PCI bus is provided and the ISA bus is not, then ISA DMA compatibility is not directly supported. One method of supporting the ISA DMA operations is to include the DMA controllers in a single PCI device. However, all DMA devices then must connect to this single PCI device, so essentially the ISA bus must be present. Other alternatives are also possible, but for various reasons not desirable.
A solution to these problems was provided by distributing the DMA controllers throughout the PC. An exemplary distributed DMA (DDMA) architecture is described in copending application serial number 08/.sub.--, entitled "Method of Having More Than Seven Channels in a Distributed DMA Architecture," assigned to Compaq Computer Corp. In that disclosure, the DDMA architecture generally includes a DMA master and at least one DMA slave channel. Each DMA slave channel provides the functionality of one channel of a conventional DMA controller. The DMA slave channels may be isolated from each other so that they can be individually coupled with particular peripheral devices requiring DMA transfers. Integrating DMA slave channels with the peripherals provides a more tightly integrated DMA architecture in which DMA requests signaled over a bus are unnecessary.
In either a conventional or distributed DMA architecture, the CPU or other programming device must configure each DMA channel before the DMA transfer can begin. Accordingly, each DMA channel includes a number of registers through which the CPU can program the channels. Some of these registers include bits corresponding to different DMA channels. For example, the Slave DMA Control Mask Register is an eight bit register as defined in Table I below.
TABLE I ______________________________________ Slave DMA Control Mask Register I/O Port Bit 7 6 5 4 3 2 1 0 ______________________________________ 000Fh not used Ch. 3 Ch. 2 Ch. 1 Ch. 0 mask mask mask mask bit bit bit bit ______________________________________
As shown, bits 3-0 of the Slave DMA Control Mask Register each represent the mask bit for a different channel. Bit 3, for example, represents the mask bit for channel 3 while bit 0 represents the mask bit for channel 0. Each DMA configuration register is updated by re-writing the entire contents of that register. Thus, if it is desired to only change the channel 2 mask bit (bit 2), the entire eight bits must be rewritten. As such, the other seven bits that do not change must be rewritten, but without changing the status of those bits. Other DMA registers, such as the Mask DMA Control Register for channels 4-7, and the Master DMA General Mask Register also include bits defined for specific channels.
A distributed DMA architecture generally includes logic for receiving the DMA programming instructions from the CPU, analyzing the instructions, and spawning "daughter cycles" to the distributed DMA controllers implicated by the programming instruction. A daughter cycle refers to a programming cycle to one of the distributed DMA controllers in response to a legacy DMA cycle from the CPU. A problem with this technique is that, in the case of programming cycles to configure DMA registers such as the Slave DMA Control Mask Register, the logic that receives the DMA programming instruction from the CPU will spawn daughter cycles to all four slave distributed DMA channels, including the channels for which the CPU is not attempting to reprogram with different data. If the CPU issues a DMA programming cycle to change the channel 3 mask reset bit (bit 3) in the Slave DMA Control Mask Register, the logic receiving that programming cycle will spawn daughter cycles to the distributed DMA controller defined for channel 3, as well as channels 0-2 even though the programming for those channels have not actually changed.
The daughter cycles typically run on a bus, such as a PCI bus, and require a certain amount of time to run. The daughter cycles to channels that have not actually been reconfigured by the CPU are unnecessary. Thus, for the foregoing reasons, a distributed DMA architecture that only spawns those daughter cycles that actually contain new configuration data would be advantageous. A computer system with such an improved distributed DMA architecture would greatly improve overall system performance as fewer daughter cycles would run on the bus. Unfortunately, to date, no such computer system is known that provides this advantage.